Assignment 3 - Predictable Multiprocessor Mapping

This website contains information on the third assignment from the multiprocessors course. The software that is used in the assignment can be found here. After installating the software, students are encouraged to read first the getting started guide before they start working on the assignment.

Updates

• (07/05/08) An update of the sofware has been released. This fixes a problem with the resource usage as printed in the HTML files. You can download the software here.

Assignment

The functionality integrated into new embedded multimedia systems is ever increasing. The Apple iPhone for example includes many different applications next to the mobile-phone functionality. It has, for example, a wide-screen LCD display that allows users to watch movies and browse through their collection of photos that are taken with the built-in camera. The phone contains also an MP3-player which allows users to listen for up-to 16 hours to their favorite music. While traveling, users can also use the phone to browse the Internet, send emails or use online navigation software such as Google-maps. It is expected that even more functions will be integrated into future embedded multimedia systems. Consumers expect that the system has a robust behavior. This requires that every application can meet its timing requirements independent of other applications that are running in the system concurrently.

This assignment considers a future multimedia system in which three time-constrained applications are mapped onto a modern Network-on-Chip-based Multiprocessor-System-on-Chip (NoC-based MP-SoC). The applications that must be mapped onto the architecture are an H.263 encoder, an H.263 decoder and an MP3 decoder. Each application has a throughput constraint that must be guaranteed independent of the other applications executing simultaneously on the NoC-based MP-SoC platform. To realize this, a platform is used that offers a predictable timing behavior to individual applications independent of other applications running on the same platform. A design-flow is available to map a throughput-constrained application onto a NoC-based MP-SoC. In this assignment, you must optimize the architecture for the following three objectives: (1) the frequency at which the architecture is running is minimized, (2) the total size of the memories in the architecture is minimized, and (3) the number of processors in the architecture is minimized. The first objective is the most important one and the third objective is the least important one.

You are given an initial architecture that runs at a frequency of 500MHz and that consists of one general purpose processor and three accelerators. These processors are connected to each other with a two by two mesh network. You are allowed to modify this initial architecture. You can add or remove processors, change memory sizes, change the interconnect structure, change scheduling settings, and change the clock frequency.

Deliverables

A report must be written about the experiments and results. It should discuss the configurations that were analyzed and it should explain why these configurations were chosen. The maximal length of this report is 4 pages (excluding figures). The report should be submitted together with the XML files that were used in the experiments. The report and the XML files that were used in the experiments must be submitted to StudyWeb before 9.00 am at June 9th.

Office hours

In case of questions, contact Sander Stuijk, s.stuijk@tue.nl, PT 9.10. Office hours are every Wednesday from 12:30-13:30 in PT 9.10, with the exception of June 4. Office hours in that week are scheduled for June 5 and June 6, both days from 12:30-13:30. For students selecting this option for assignment 3, an introductory hour to get started with the assignment is scheduled on April 23, from 12:30-13:30, PT 9.10.